This paper presents a systematic method of designing and microprogramming fast signal processors (SP's) while optimally utilizing the inherent parallelism of a given algorithm. The method employs graph-theoretical concepts and scheduling techniques from "project management" and permits an easy evaluation of the following key design parameters: i) the lower bound on the algorithm duration (Tmp) for given speeds of the arithmetic components in a signal processor, ii) the minimum arithmetic hardware requirements necessary for the completion of the algorithm within the time Tmp, and iii) the optimum algorithm schedule and the corresponding minimum attainable duration Tat, when constraints on the available SP resources are imposed. In combination with the data-flow analysis and resource allocation, the scheduling procedure permits the influence of the SP architecture on the schedule to be modeled and the basic architectural features of the SP to be determined. The results also provide information for automatic microprogram generation and for the assessment and comparison of signal processor performance and algorithm speeds. The synthesis of architectures is based on an "ideal, data-flow driven signal processor" that is introduced in the paper. The proposed design approach is demonstrated on various digital-filter algorithms.