A technique is presented for implementing a finite impulse response (FIR) digital filter in a residue number system (RNS). For many years residue number coding has been recognized as a system which provides a capability for the implementation of high speed multiplication and addition. The advantages of residue coding for the design of high speed FIR filters result from the fact that an FIR requires only the high speed residue operations, i.e., addition and multiplication, while not requiring the slower RNS operations of division or sign detection. A new hardware implementation of the Chinese Remainder Theorem is proposed for an efficient translation of residue coded outputs into natural numbers. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters. An RNS implementation of a 64th-order dual bandpass filter is compared with several alternative filter structures to illustrate tradeoffs between speed and hardware complexity.