This paper presents an EIA-709.1 protocol architecture that can alleviate the burden of data communications in the Neuron chip. The proposed protocol is implemented with partly hardware and partly software. The physical layer and the MAC layer of the EIA-709.1 protocol are implemented with hardware. The upper link layer of the EIA-709.1 protocol is implemented with software. We verified the commercial feasibility of the proposed system through the power line tests with the existing LonWorks network. As a result, it is concluded that the proposed architecture provides flexibility and cost benefit for the system implementations.