By Topic

A novel scan architecture for power-efficient, rapid test [sequential circuits]

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
2 Author(s)
O. Sinanoglu ; Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA ; A. Orailoglu

Author(s)

O. Sinanoglu
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu