Automated bus generation for multiprocessor SoC design
Kyeong Keol Ryu
Mooney, V.J., III
Sch. of Electr. & Comput. Eng., Georgia Inst. of Technol., Atlanta, GA, USA;
This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publication Date: Nov. 2004
Volume: 23,
Issue: 11
On page(s): 1531- 1549
ISSN: 0278-0070
INSPEC Accession Number: 8214442
Digital Object Identifier: 10.1109/TCAD.2004.835119
Posted online: 2004-11-01 11:50:08.0
Abstract
The performance of a multiprocessor system heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custom bus system for a multiprocessor system-on-a-chip (SoC). Our bus-synthesis tool, which we call BusSynth, uses this methodology to generate five different bus systems as examples: 1) bidirectional first-in first-out bus architecture; 2) global bus architecture (GBA) version I; 3) GBA version III; 4) hybrid bus architecture (Hybrid); and 5) split bus architecture. We verify and evaluate the performance of each bus system in the context of three applications: an orthogonal frequency division multiplexing wireless transmitter, an MPEG2 decoder, and a database example. Our methodology gives the designer a great benefit in the fast-design space exploration of bus architectures across a variety of performance impacting factors such as bus types, processor types, and software programming style. In this paper, we show that BusSynth can generate buses that, when compared to a typical general GBA, achieve superior performance (e.g., 41% reduction in execution time in the case of a database example). In addition, the bus architecture generated by BusSynth is designed in a matter of seconds instead of weeks for the hand design of a custom bus system.
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