Full-wave PEEC time-domain method for the modeling of on-chipinterconnects
Restle, P.J.
Ruehli, A.E.
Walker, S.G.
Papadopoulos, G.
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY;
This paper appears in: Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publication Date: Jul 2001
Volume: 20,
Issue: 7
On page(s): 877-886
ISSN: 0278-0070
References Cited: 9
CODEN: ITCSDI
INSPEC Accession Number: 6971871
Digital Object Identifier: 10.1109/43.931029
Posted online: 2002-08-07 00:27:54.0
Abstract
With the advances in the speed of high-performance chips,
inductance effects in some on-chip interconnects have become
significant. Specific networks such as clock distributions and other
highly optimized circuits are especially impacted by inductance. Several
difficult aspects have to be overcome to obtain valid waveforms for
problems where inductances contribute significantly. Mainly, the
geometries are very complex and the interactions between the capacitive
and inductive currents have to be taken into account simultaneously. In
this paper, we show that a full-wave partial element equivalent circuit
method, which includes the delays among the partial elements, leads to
an efficient solver enabling the analysis of large meaningful problems.
Applying this method to several examples leads to helpful insights for
realistic very large scale integration wiring problems. It is shown in
this paper that the impact overshoot, reflections, and inductive
coupling are critical for the design of critical on-chip interconnects
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