Naffziger, S.
Hewlett-Packard Co., Fort Collins, CO;
This paper appears in: Solid-State Circuits Conference, 1996. Digest of Technical Papers. 42nd ISSCC., 1996 IEEE International
Publication Date: Feb 1996
On page(s): 362-363
Meeting Date: 02/08/1996 - 02/10/1996
Location: San Francisco, CA, USA
ISSN: 0193-6530
ISBN: 0-7803-3136-2
References Cited: 6
INSPEC Accession Number: 5316842
Digital Object Identifier: 10.1109/ISSCC.1996.488718
Posted online: 2002-08-06 20:22:36.0
Abstract
A sub-nanosecond 64 b adder in 0.5 μm CMOS forms the basis for
the integer and floating point execution units. Integrating dual-rail
dynamic CMOS and use of Ling's equations, the adder is composed of 7k
FETs in 0.246 mm2 and performs a full 64 b add, operands to
result in <1 ns (7 fanout of 4 inverter delays) under nominal
conditions
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