Deterministic addressing of nanoscale devices assembled at sublithographic pitches
DeHon, A.
Comput. Sci. Dept., California Inst. of Technol., Pasadena, CA, USA;
This paper appears in: Nanotechnology, IEEE Transactions on
Publication Date: Nov. 2005
Volume: 4,
Issue: 6
On page(s): 681- 687
ISSN: 1536-125X
INSPEC Accession Number: 8649039
Digital Object Identifier: 10.1109/TNANO.2005.858587
Posted online: 2005-11-07 09:51:55.0
Abstract
Multiple techniques have now been proposed using random addressing to build demultiplexers which interface between the large pitch of lithographically patterned features and the smaller pitch of self-assembled sublithographic nanowires. At the same time, the relatively high defect rates expected for molecular-sized devices and wires dictate that we design architectures with spare components so we can map around defective elements. To accommodate and mask both of these effects, we introduce a programmable addressing scheme which can be used to provide deterministic addresses for decoders built with random nanoscale addressing and potentially defective wires. We describe how this programmable addressing scheme can be implemented with emerging, nanoscale building blocks and show how to build deterministically addressable memory banks. We characterize the area required for this programmable addressing scheme. For 2048×2048 memory banks, the area overhead for address correction is less than 33%, delivering net memory densities around 1011 b/cm2.
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