Electronic Computers, IRE Transactions on
This Transactions ceased publication in 1962. The current retitled publication is
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Stability of a Method of Smoothing in a Digital Control Computer
Feb17 2010 
Review of Electronic Computer Progress During 1954
Feb17 2010 
A Digital Computer for Use in an Operational Flight Trainer
Feb17 2010 
An AlphaState Finite Automaton for Multiplication by Alpha
Feb17 2010 
A Diode Multiplexer for Analog Voltages
Feb17 2010
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The CORDIC Trigonometric Computing Technique
Aug25 2009 
Computer Multiplication and Division Using Binary Logarithms
Aug25 2009 
SignedDigit Numbe Representations for Fast Parallel Arithmetic
Aug25 2009 
An Algorithm for Path Connections and Its Applications
Aug25 2009 
On the Encoding of Arbitrary Geometric Configurations
Aug25 2009
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1. The CORDIC Trigonometric Computing Technique
Publication Year: 1959 , Page(s): 330  334
Cited by: Papers (652)  Patents (88)The COordinate Rotation DIgital Computer(CORDIC) is a specialpurpose digital computer for realtime airborne computation. In this computer, a unique computing technique is employed which is especially suitable for solving the trigonometric relationships involved in plane coordinate rotation and conversion from rectangular to polar coordinates. CORDIC is an entiretransfer computer; it contains a special serial arithmetic unit consisting of three shift registers, three addersubtractors, and special interconnections. By use of a prescribed sequence of conditional additions or subtractions, the CORDIC arithmetic unit can be controlled to solve either set of the following equations: Y' = K(Y cosÂ¿ + X sinÂ¿) X' = K(X cosÂ¿  Y sinÂ¿), or R = KÂ¿X2 + Y2 Â¿ = tan1 Y/X, where K is an invariable constant. This special arithmetic unit is also suitable for other computations such as multiplication, division, and the conversion between binary and mixed radix number systems. However, only the trigonometric algorithms used in this computer and the instrumentation of these algorithms are discussed in this paper. View full abstract»

2. Computer Multiplication and Division Using Binary Logarithms
Publication Year: 1962 , Page(s): 512  517
Cited by: Papers (101)  Patents (10)A method of computer multiplication and division is proposed which uses binary logarithms. The logarithm of a binary number may be determined approximately from the number itself by simple shifting and counting. A simple add or subtract and shift operation is all that is required to multiply or divide. Since the logarithms used are approximate there can be errors in the result. An error analysis is given and a means of reducing the error for the multiply operation is shown. View full abstract»

3. SignedDigit Numbe Representations for Fast Parallel Arithmetic
Publication Year: 1961 , Page(s): 389  400
Cited by: Papers (456)  Patents (18)This paper describes a class of number representations which are called signeddigit representations. Signeddigit representations limit carrypropagation to one position to the left during the operations of addition and subtraction in digital computers. Carrypropagation chains are eliminated by the use of redundant representations for the operands. Redundancy in the number representation allows a method of fast addition and subtraction in which each sum (or difference) digit is the function only of the digits in two adjacent digital positions of the operands. The addition time for signeddigit numbers of any length is equal to the addition time for two digits. The paper discusses the properties of signeddigit representations and arithmetic operations with signeddigit numbers: addition, subtraction, multiplication, division and roundoff. A brief discussion of logical design problems for a signeddigit adder concludes the presentation. View full abstract»

4. An Algorithm for Path Connections and Its Applications
Publication Year: 1961 , Page(s): 346  365
Cited by: Papers (417)  Patents (14)The algorithm described in this paper is the outcome of an endeavor to answer the following question: Is it possible to find procedures which would enable a computer to solve efficiently pathconnection problems inherent in logical drawing, wiring diagramming, and optimal route finding? The results are highly encouraging. Within our framework, we are able to solve the following types of problems: 1) To find a path between two points so that it crosses the least number of existing paths. 2) To find a path between two points so that it avoids as much as possible preset obstacles such as edges. 3) To find a path between two points so that the path is optimal with respect to several properties; for example, a path which is not only one of those which cross the fewest number of existing paths, but, among these, is also one of the shortest. The minimaldistance solution has been programmed on an IBM 704 computer, and a number of illustrations are presented. The class of problems solvable by our algorithm is given in a theorem in Section III. A byproduct of this algorithm is a somewhat remote, but unexpected, relation to physical optics. This is discussed in Section VI. View full abstract»

5. On the Encoding of Arbitrary Geometric Configurations
Publication Year: 1961 , Page(s): 260  268
Cited by: Papers (254)  Patents (20)A method is described which permits the encoding of arbitrary geometric configurations so as to facilitate their analysis and manipulation by means of a digital computer. It is shown that one can determine through the use of relatively simple numerical techniques whether a given arbitrary plane curve is open or closed, whether it is singly or multiply connected, and what area it encloses. Further, one can cause a given figure to be expanded, contracted, elongated, or rotated by an arbitrary amount. It is shown that there are a number of ways of encoding arbitrary geometric curves to facilitate such manipulations, each having its own particular advantages and disadvantages. One method, the socalled rectangulararray type of encoding, is discussed in detail. In this method the slope function is quantized into a set of eight standard slopes. This particular representation is one of the simplest and one that is most readily utilized with presentday computing and display equipment. View full abstract»

6. CarrySelect Adder
Publication Year: 1962 , Page(s): 340  346
Cited by: Papers (89)  Patents (16)A large, extremely fast digital adder with sum selection and multipleradix carry is described. Boolean expressions for the operation are included. The amount of hardware and the logical delay for a 100bit ripplecarry adder and a carryselect adder are compared. The adder system described increases the speed of the addition process by reducing the carrypropagation time to the minimum commensurate with economical circuit design. The problem of carrypropagation delay is overcome by independently generating multipleradix carries and using these carries to select between simultaneously generated sums. In this adder system, the addend and augend are divided into subaddend and subaugend sections that are added twice to produce two subsums. One addition is done with a carry digit forced into each section, and the other addition combines the operands without the forced carry digit. The selection of the correct, or true, subsum from each of the adder sections depends upon whether or not there actually is a carry into that adder section. View full abstract»

7. An optimum character recognition system using decision functions
Publication Year: 1957 , Page(s): 247  254
Cited by: Papers (67)  Patents (1)The character recognition problem, usually resulting from characters being corrupted by printing deterioration and/or inherent noise of the devices, is considered from the viewpoint of statistical decision theory. The optimization consists of minimizing the expected risk for a weight function which is preassigned to measure the consequences of system decisions As an alternative minimization of the error rate for a given rejection rate is used as the critenon. The optimum recogition is thus obtained. The optimum system consists of a conditionalprobability densisities computer; character channels, one for each character; a rejection channel; and a comparison network. Its precise structure and and ultimate performance depend essentially upon the signals and noise structure. Explicit examples for an additive Gaussian noise and a ``cosine'' noise are presented. Finally, an errorfree recognition system and a possible criterion to measure the character style and deteriortation are presented. View full abstract»

8. The Residue Number System
Publication Year: 1959 , Page(s): 140  147
Cited by: Papers (78)  Patents (5)A novel number system called the residue number system is developed from the linear congruence viewpoint. The residue number system is of particular interest because the arithmetic operations of addition, subtraction and multiplication may be executed in the same period of time without the need for carry. The main difficulties of the residue code pertain to the determination of the relative magnitude of two residue representations, and to the division process. A discussion of the arithmetic operations and the conversion process required to convert from a residue code to a weighted code is given. It is concluded that in its present state the residue code is probably not suitable for general purpose computation but is suitable for a special class of control problems. Further research in both components and arithmetic is required if a residue code suitable for general purpose computation is to be obtained. View full abstract»

9. Regular Expressions and State Graphs for Automata
Publication Year: 1960 , Page(s): 39  47
Cited by: Papers (48)  Patents (2)Algorithms are presented for 1) converting a state graph describing the behavior of an automaton to a regular expression describing the behavior of the same automaton (section 2), and 2) for converting a regular expression into a state graph (sections 3 and 4). These algorithms are justified by theorems, and examples are given. The first section contains a brief introduction to state graphs and the regularexpression language. View full abstract»

10. The Logic of Bidirectional Binary Counters
Publication Year: 1957 , Page(s): 1  4
Cited by: Papers (2)The counters without shorttime internal memory, conceived by Bigelow, disclosed by Ware, and extended by Brown, are discussed from the standpoint of their respective logic. It is shown that the (selfinstructed) bidirectional1 counter of Brown has a more rigorous logic than the unidirectional counter of Ware; the operation of Brown's bidirectional counter being subjected to the only restriction that its speed be compatible with the operating speed of its individual toggles, whereas the operation of Ware's counter is predicated upon the existence of unspecified buffering states in the input of each stage, to prevent runaway conditions. These buffering states, which occur naturally in Brown's bidirectional counter, can be provided explicitly in unidirectional counters by replacing the two transfer circuits of Ware's counter stage, which are controlled only by one toggle of the preceding stage, by two of the four transfer circuits of Brown's bidirectional counter stage, all four of which are controlled by both toggles of the preceding stage. This paper introduces the viewpoint that a bidirectional counter of Brown's type is a counter in which the state of one toggle of each stage determines which toggle of the next stage is master, while the state of the other toggle of each stage determines whether the slave of the next stage shall be like or unlike the master. This viewpoint permits a succinct discussion of the several possible interstage connections, and of the several counting codes obtained for each connection. View full abstract»

11. A New Class of Digital Division Methods
Publication Year: 1958 , Page(s): 218  222
Cited by: Papers (123)  Patents (12)This paper describes a class of division methods best suited for use in digital computers with facilities for floating point arithmetic. The division methods may be contrasted with conventional division procedures by considering the nature of each quotient digit as generated during the division process. In restoring division, each quotient digit has one of the values 0,1, . . . , r Â¿1, for an arbitrary integer radix r. In nonrestoring division, each quotient digit has one of the values Â¿(rÂ¿1),. . ., Â¿1, +1, . . ., +(rÂ¿1). For the division methods described here, each quotient digit has one of the values Â¿n, Â¿(nÂ¿1), . . ., Â¿1, 0, 1, . . . nÂ¿1, n, where n is an integer such that Â¿(r Â¿1)Â¿nÂ¿rÂ¿1. A method for serial conversion of the quotient digits to conventional (restoring) form is given. Examples of new division procedures for radix 4 and radix 10 are given. View full abstract»

12. An Automatic SelfChecking and FaultLocating Method
Publication Year: 1962 , Page(s): 649  654
Cited by: Papers (1)A method is described for designing systems which automatically check themselves and give indications by which internal faults can be located quickly and accurately. Relatively little circuitry is required, and the performance of the test and fault location are easy. The proposed method entails the arrangement of a sequence of events which can be completed properly only if no malfunction exists. Applied to a 555transistor digital system, the method yielded the following results: An indicatorlight test and a 2.27second selfcheck provide 100 per cent confidence that the device is in perfect order. 90 per cent of the trouble indications isolate faults to one or two plugin cards, each holding one to six transistor circuits. This checking capability is provided by only 182. per cent of the transistors in the system. View full abstract»

13. Minimizing the Number of States in Incompletely Specified Sequential Switching Functions
Publication Year: 1959 , Page(s): 356  367
Cited by: Papers (107)Given a sequential switching function in the form of a flow table in which some of the entries are unspecified, the problem of reducing the number of rows in that flow table is extremely complex, and cannot, in general, be solved by any simple extension of the methods used for completely specified functions. An analysis of the problem is presented, and a partially enumerative solution is evolved. A rough indication of the efficiency of the given procedures may be obtained from the fact that these techniques have been successfully applied to approximately two dozen tables ranging up to about 15 rows. No solution required more than two hours. View full abstract»

14. TimeDelay Circuits
Publication Year: 1955 , Page(s): 74
Cited by: Papers (4)First Page of the ArticleView full abstract» 
15. Design of Memory Sense Amplifiers
Publication Year: 1962 , Page(s): 236  253
Cited by: Papers (3)A fundamental problem in the design of fast (4 to 6 Â¿sec) word oriented memories using S1 core material is the realization of a sensing amplifier which has the multitude of required properties. The sense amplifier is usually required to provide stable gain for bipolarity signals, to introduce a negligible delay into the signal path, to avoid dc level shift, to recover within a short time following the enable (or inhibit) noise, to provide a stable discrimination level, etc. Although many sense amplifier designs have appeared in the literature, none, to the authors' knowledge, are eminently suitable for a 4 to 6Â¿sec memory under the condition of ``worst case input pattern''Â¿a long sequence of unipolarity pulses interspaced with ``blasts'' of enable noise. The basic requirements for a sense amplifier suitable for a word oriented memory in conjunction with a required memory cycle are discussed. This newly developed sense amplifier and its operation and design are presented. Emphasis is placed on the evolution of the techniques and circuits presented, and several other approaches pursued during the design are also described. The authors also comment on possible future approaches to the sensing problem. View full abstract»

16. A Survey of Regular Expressions and Their Applications
Publication Year: 1962 , Page(s): 324  335
Cited by: Papers (9)This paper is an exposition of the theory of regular expressions and its applications to sequential circuits. The results of several authors are presented in a unified manner, pointing out the similarities and differences in the various treatments of the subject. Whenever possible, the terminology and notation of sequential circuit theory are used. The topics presented include: the relation of regular expressions to sequential circuits; algorithms for constructing sequential circuits and state diagrams corresponding to a given regular expression; methods for obtaining a regular expression from a state diagram of a sequential circuit, improper state diagrams, algebraic properties of regular expressions, and applications to codes. View full abstract»

17. Skip Techniques for HighSpeed CarryPropagation in Binary Arithmetic Units
Publication Year: 1961 , Page(s): 691  698
Cited by: Papers (53)  Patents (2)After a very brief summary of the various wellknown methods of expediting carrypropagation in binary arithmetic units, the paper discusses and develops the ``anticipatedcarry'' or ``carryskip'' technique originally due in decimal form to Babbage, much used in mechanical calculators and lately revived for use in binary units. Various degrees of refinement are possible. It appears that for a given expenditure, the technique results in a unit which is simpler and faster than those using one of the other techniques. Conversely in order to attain a given speed with given circuit elements, the skip technique appears to minimize the equipment requirement among the known speedup techniques. View full abstract»

18. ConditionalSum Addition Logic
Publication Year: 1960 , Page(s): 226  231
Cited by: Papers (165)  Patents (24)Conditionalsum addition is a new mechanism for parallel, highspeed addition of digitallyrepresented numbers. Its design is based on the computation of ``conditional'' sums and carries that result from the assumption of all the possible distributions of carries for various groups of columns. A rapidsequence mode of operation provides an addition rate that is invariant with the lengths of the summands. Another advantage is the possibility of realizing the adder with ``integrated devices'' or ``modules.'' The logic of conditionalsum addition is applicable to all positive radices, as well as to multisummand operation. In a companion paper, a comparison of several adders shows that, within a set of stated assumptions, conditionalsum addition is superior in certain respects, including processing speed. View full abstract»

19. A Method for Resolving Multiple Responses in a Parallel Search File
Publication Year: 1961 , Page(s): 718  722
Cited by: Papers (14)  Patents (1)It is possible to build memories in which the contents of all registers are tested simultaneously, and in which there is a single indication of the presence or absence of any number of positive responses to the test criterion. A method is described for separately identifying the members of a set of responses by presenting sequences of tests which generate an identification number for each member. The testing algorithm is easily mechanized, and the number of tests required per item is approximately proportional to the logarithm of the number of file registers. The method also may be used to search for items with contents falling within arbitrary numerical ranges. View full abstract»

20. Arithmetic Operations for Digital Computers Using a Modified Reflected Binary Code
Publication Year: 1959 , Page(s): 449  458
Cited by: Papers (3)  Patents (1)The reflected binary or Gray code has been used chiefly in analogtodigital conversion devices because its code sequences, representing any two consecutive integral numbers, differ in only one digit. This paper presents a method for performing the arithmetic operations of addition, subtraction, multiplication, and division using a modified reflected binary code. The modification for integral numbers is essentially the addition of an even parity check bit to the Gray code representation. This facilitates both the arithmetic operations and the detection of errorsÂ¿in the arithmetic process as well as in transmission. An adder using this code requires circuitry which is more complex than that of a conventional binary adder by a factor of about two or three. However, the adder can be used also for subtraction with little additional circuitry and without complementation. In applications where reliability requirements justify the extra circuitry needed for arithmetic error detection, the modified reflected binary code may compare favorably with the conventional binary. View full abstract»

21. The Neuristor
Publication Year: 1960 , Page(s): 370  371
Cited by: Papers (4)First Page of the ArticleView full abstract» 
22. BIDEC  A BinarytoDecimal or DecimaltoBinary Converter
Publication Year: 1958 , Page(s): 313  316
Cited by: Papers (9)Simple, highspeed devices to convert binary, binary coded octal, or Gray code numbers to binary coded decimal numbers or vice versa is described. Circuitry required is four shift register stages per decimal digit plus one 30diode network per decimal digit. In simple form the conversion requires two operations per binary bit but is theoretically capable of working at one operation per bit. View full abstract»

23. UnitDistance ErrorChecking Codes
Publication Year: 1958 , Page(s): 179  180
Cited by: Papers (13)First Page of the ArticleView full abstract» 
24. Error Detecting and Correcting Binary Codes for Arithmetic Operations
Publication Year: 1960 , Page(s): 333  337
Cited by: Papers (39)  Patents (1)The most important property of the codes derived in this paper is that two numbers, i and j, have coded forms, C(i) and C(j) that when added in a conventional binary adder, give a sum C(i)+C(j) that differs from C(i+j), the code for the sum, by (at most) an additive constant. This makes possible the detection and/or correction of errors committed by the arithmetic element of a computer. In addition, messages can be coded and decoded and errors can be detected and corrected by arithmetic procedures, making it possible to elininate some or all of the specialpurpose equipment usually associated with errordetecting or correcting codes. This property may make these codes useful for data transmission as well as for computation. View full abstract»

25. A TimeSequential Tabular Analysis of FlipFlop Logical Operation
Publication Year: 1957 , Page(s): 72  74
Cited by: Papers (1)In examining flipflop response the principal concern of the logical designer is to find what input signals must be applied to the flipflop in order to produce the output conditions that are desired. Equation methods of analysis and a timesequential tabular method of analysis are described, and some advantages of the tabular method are pointed out. View full abstract»

26. Esaki Diode HighSpeed Logical Circuits
Goto, E. ; Murata, K. ; Nakazawa, K. ; Nakagawa, K. ; MotoOka, T. ; Matsuoka, Y. ; Ishibashi, Y. ; Ishida, H. ; Soma, T. ; Wada, E.Publication Year: 1960 , Page(s): 25  29
Cited by: Papers (55)  Patents (2)Logical circuits using Esaki diodes, and which are based on a principle similar to parametron (subharmonic oscillator element) circuits, are described. Two diodes are used in series to form a basic element called a twin, and a binary digit is represented by the polarity of the potential induced at the middle point of the twin, which is controlled by the majority of input signals applied to the middle point. Unilateral transmission of information in circuits consisting of cascaded twins is achieved by dividing the twins into three groups and by energizing each group one after another in a cyclic manner. Experimental results with the clock frequency as high as 30 mc are reported. Also, a delayline dynamic memory and a nondestructive memory in matrix form are discussed. View full abstract»

27. A HighSpeed Analog to Digital Converter
Publication Year: 1959 , Page(s): 31  35
Cited by: Papers (4)An electronic voltage encoder has been developed which converts analog voltages to their corresponding parallel seven binarydigit representations at a 50kc encoding rate. The encoder is capable of being timeshared by any number of 050volt range inputs. Performance tests indicate that the present design may be capable of eight binarydigit conversions at encoding rates as high as 80 kc. Either more precise conversions or higher encoding rates may be obtained at the expense of the other by cascading more or less of the identical onedigit encoder stages which constitute the analog to digital converter. View full abstract»

28. Improving the Performance of the SenseAmplifier Circuit Through PreAmplification Strobing and NoiseMatched Clipping
Publication Year: 1962 , Page(s): 677  683
Cited by: Papers (3)For the improvement of the performance of the senseamplifier circuit for conventional ferritecore memories, the principles of preamplification strobing and noisematched clipping are proposed and discussed. A circuit incorporating these principles and achieving notable reliability and economy is described. The circuit is suitable for working with short cycle times and low signaltonoise ratio values and can be used to process matrices of sizes considerably larger than 4096 cores. View full abstract»

29. Generalized Parity Checking
Publication Year: 1958 , Page(s): 207  213
Cited by: Papers (15)The usual definition given for the parity check is unwieldy and not particularly suited for the analysis or the study of the arithmetic properties of parity checking. The definition of parity by means of congruences provides a convenient mathematical basis for the concepts of the parity check. In this paper congruence notation is used to generalize the concepts of parity to include nonbase two number systems. Consideration is given to the cases where the check base is equal to the number base, and where it is not equal to the number base. The arithmetic properties of each case are considered by means of congruences. View full abstract»

30. A Truth Table Method for the Synthesis of Combinational Logic
Publication Year: 1961 , Page(s): 604  615
Cited by: Papers (12)This paper describes a method for synthesizing a switching function directly from its: ruth table. A switching function is defined as any mapping of a set of binary input combinations onto 0 and 1. Hence, the procedures apply equally well to the don't care cases. The method rests on the concept alogically passive function (LPF). Roughly speaking, an LPF is a truth table which can be realized with only AND and OR gatesÂ¿no inverters. Techniques are described for 1) making a function logically passive, 2) eliminating rows and columns from the truth table of an LPF, 3) synthesizing an LPF in a twolevel irredundant form, 4) expanding LPF's and 5) synthesizing LPF's with 3input majority gates. The underlying methods are quite straightforward and appear to be particularly well suited for mechanization on a digital computer. View full abstract»

31. The Reduction of Redundancy in Solving Prime Implicant Tables
Publication Year: 1962 , Page(s): 473  482
Cited by: Papers (12)This paper is primarily concerned with finding, in the most efficient possible way, the set of all solutions to a cyclic prime implicant table. (A solution is a set of rows such that every column contains at least one marked entry in a row belonging to the set and such that no row can be deleted from the set without destroying this property.) Extensive use is made of the relationship between this and the problem of efficiently reducing a Boolean frontal function from the form of a product of sums of single literals to a sum of products. The transformation methods commonly in use today have the disadvantage that they tend to introduce duplicate and redundant products. (A redundant product includes at least one row which can be removed, and the remaining rows will still constitute a solution.) Several methods which appreciably reduce the number of such redundancies are presented. One of these methods (called row branching), applies repeatedly the algebraic transformation f = af(Â¿ = 1) + f(Â¿= 0) where Â¿ is the Boolean variable corresponding to a row of the table, and f is the function corresponding to the given table. The mechanism by which a redundant solution is generated is described. The paper includes other useful transformation procedures such as, for example, a tabular method in which redundancies are avoided systematically at each step. View full abstract»

32. DiodeSteered MagneticCore Memory
Publication Year: 1959 , Page(s): 474  478
Cited by: Papers (2)This paper describes techniques which take advantage of word arrangement to make possible large, highspeed magneticcore memories at moderate cost. Economy is obtained by means of a twocoordinate selection system using diffused junction rectifiers as steering diodes. By taking advantage of the relatively slow recovery time of these rectifiers, automatic rewrite selection is obtained in a similar sense to that provided by a biased switch core. The familiar ``inhibit'' line is eliminated, reducing the memory array to a twowire configuration. And finally, the customary core array geometry is rearranged to facilitate winding the digit wire as a balanced twistedpair transmission line so as to eliminate the effect of postwrite disturb. View full abstract»

33. Flight Simulation of Orbital and ReEntry Vehicles
Publication Year: 1962 , Page(s): 555  563
Cited by: Papers (1)The three translational and three rotational equilibrium equations for an orbital vehicle subject to aerodynamic and jet reaction forces are derived using a modified flightpath axis system for the translational equations. The dependent variables of the system are horizontal velocity component, vertical velocity component, and flightpath heading angle. Theresulting equations are shown to have advantages for computer mechanization over alternative axis systems for the translational equations. Complete equations for determining vehicle orientation, instantaneous latitude and longitude, angle of attack, angle of sideslip, areodynamic forces and moments, etc., are presented. Modifications in the translational equations which allow direct solution by an analog computer are also given. Analog computer mechanization of these equations in both real and fast time is described, including a novel technique for division which preserves favorable multiplier scaling. Specific machine results are presented which demonstrate accurate solution of closesatellite trajectories, including reentry from satellite altitudes to sea level. With no change in circuit or scaling the same computer mechanization yields zerodrag orbits which close within several hundred feet of altitude. View full abstract»

34. Complexity in Electronic Switching Circuits
Publication Year: 1956 , Page(s): 15  19
Cited by: Papers (26)The complexity of an electronic switching circuit is defined in a sufficiently general way so that most definitions which are presently used may be included. If Â¿(p, q) is the complexity of a p input q output circuit which has been minimized then we may define E(p, q) as the maximum of Â¿(p, q) over all p input, q output circuits. In spite of the generality of the definition of complexity one may obtain the following inequality which gives upper and lower bounds on this maximum complexity: C12r/rÂ¿E(p, q)Â¿C22r/r where r = p+log2 q. In this expression C1 and C2 are constants independent of p and q which depend upon the definition of complexity. These theoretical bounds are compared with those obtained from a few known circuiit designs. View full abstract»

35. Odd Binary Asynchronous Counters
Publication Year: 1956 , Page(s): 12  15This paper describes a general method for modifying conventional binary asynchronous counters such that the counting register advances by any desired odd integer for each received count. The pertinent design features of conventional additive and subtractive asynchronous counters are reviewed. Simplification of the design of a counter which advances by an odd integer is achieved through use of a set of alternately additive and subtractive subcounters. An example of the logical design of a counter which advances by 13 is presented. View full abstract»

36. A Recognition Method Using Neighbor Dependence
Publication Year: 1962 , Page(s): 683  690
Cited by: Papers (25)Within the framework of an early paper1 which considers character recognition as a statistical decision problem, the detailed structure of a recognition system can be systematically derived from the functional form of probability distributions. A binary matrix representation of signal is used in this paper. A nearestneighbor dependence method is obtained by going beyond the usual assumption of statistical independence. The recognition network consists of three levelsÂ¿a layer of AND gates, a set of linear summing networks in parallel, and a maximum selection circuit. Formulas for weights or recognition parameters are also derived, as logarithms of ratios of conditional probabilities. These formulas lead to a straightforward procedure of estimating weights from sample characters, which are then used in subsequent recognition. Simulation of the recognition method is performed on a digital computer. The program consists of two main operationsestimation of parameters from sample characters, and recognition using these estimated values. The experimental results indicate that the effect of neighbor dependence upon recognition performance is significant. On the basis of a rather small sample of 50 sets of handprinted alphanumeric characters, the recognition performance of the nearestneighbor method compares favorably with other recognition schemes. View full abstract»

37. An experiment in musical composition
Publication Year: 1957 , Page(s): 175  182
Cited by: Papers (6)The highorder probabilities of element sequences can be determined from a sample of linear structures and can be used for synthesis of new structures. From theoretical considerations one can identify the qualitative conditions for satisfactory output. The theoretical concepts can be tested and quantitative parameters determined by experiment. Such an experiment has been performed by analyzing written music and by testing the analysis through the synthesis of new musical compositions, using a digital computer. A sample of 37 melodies was analyzed for the probabilities of the elements, element pairs (digrams), trigrams, and so on to the eighth order. The tables derived were used for the synthesis of original melodies by a random process. The theory and the experimental verification are considered in detail. The experimental results presented include comparative statistics of the successful syntheses using each of the eight orders of analysis, examples of melodies generated by low, medium, and highorder synthesis, and confirmation of degeneracy and other effects predicted by the theory. View full abstract»

38. A Computer for Solving Linear Simultaneous Equations Using the Residue Number System
Publication Year: 1962 , Page(s): 164  173
Cited by: Papers (1)The design of a specialpurpose digital computer for solving simultaneous equations which operates with numbers coded in the residue number system is described. Since addition, subtraction or multiplication can be done in onebit time using this coding, GaussSeidel iteration can be done in a very fast and efficient manner. The computer has been arbitrarily designed to solve dense systems of equations with as many as 128 unknowns and sparse systems with as many as 512 unknowns. Operating at a 500kc clock rate, the computer would be able to perform one complete iteration on a system with 128 unknowns 30 times faster than an IBM 704. Using a 7 digit residue code requiring a 42bit word, the computer would provide solutions of up to 4 significant figures. By using the best presently obtainable components, computing speed can be increased by a factor of 5. The size of the system which can be handled and the number of significant digits which can be obtained in the solutions can also be extended if desired. The speed of computation obtained with this computer is made possible by the combination of the onebittime arithmetic operations obtainable with residue numbers, the high data rate possible with a magnetic drum, and the sequential nature of the GaussSeidel iteration procedure. The digital techniques which have been developed to realize a computer of this type include methods of encoding decimal numbers into residue representation, rescaling residue numbers, and decoding residue numbers into binary coded decimal form. View full abstract»

39. Some Properties of Boolean Equations
Publication Year: 1958 , Page(s): 291  298
Cited by: Papers (3)Solubility conditions for a set of Boolean equations are established, first with respect to one variable, then with respect to all variables. By consideration of relations between minimal terms, a simple matrix form is deduced for Boolean equations. Using finite group theory and the properties of the characteristic equation of the matrix, a classification is introduced for Boolean mappings and their iterations, to which corresponds a classification of sequential machines. View full abstract»

40. Comparison of Saturated and Nonsaturated Switching Circuit Techniques
Publication Year: 1960 , Page(s): 161  175
Cited by: Papers (1)The concept that the junction transistor is a chargecontrolled current source is reviewed. Saturated operation and nonsaturated operation are defined on the basis of minority and majority carrier distributions in the base region. Several common emitter switching circuits are analyzed. The switching efficiency, a figure of merit based on the charge storage properties of the transistor, is introduced. Saturated and nonsaturated operation are compared on the basis of switching efficiency, transient waveforms, stability of the voltage levels, power dissipation, noise rejection and suppression ablity, and circuit complexity. Currentlyused antisaturation techniques are discussed. View full abstract»

41. Approximations for the Demagnetizing Factors of Hollow Cylinders Represented by Confocal Hollow Prolate Spheroids
Publication Year: 1962 , Page(s): 789First Page of the ArticleView full abstract» 
42. Functional Notation for NOR and NAND Networks
Publication Year: 1961 , Page(s): 778
Cited by: Papers (1)First Page of the ArticleView full abstract» 
43. RealTime Computation and Recursive Functions Not RealTime Computable
Publication Year: 1962 , Page(s): 753  760
Cited by: Papers (16)As an attempt to investigate a general theory of realtime computability in digital computers, a subclass of Turing machines is formally introduced together with some classes of functions that are computable by them in real time. Then the existence is established of a class of recursive functions that are not computable in real time by use of a class of machines, no matter how general we make the machines subject to a given constraint. View full abstract»

44. Proposed IRE Standards for Analog Computers
First Page of the ArticleView full abstract» 
45. Encoding and Decoding for Cyclic Permutation Codes
Publication Year: 1962 , Page(s): 507  511
Cited by: Papers (1)Maximumlikelihood encoding and decoding procedures are presented for cyclic permutation errorcorrecting codes. These procedures take advantage of the cyclic permutation structure, and are applicable to all such codes. On the other hand, familiar paritychecking procedures are applicable only to those few cyclic permutation codes which are group codes. A comparison of the two different procedures for the group code case shows that they are roughly comparable in complexity. View full abstract»

46. Bilateral Switching Using Nonsymmetric Elements
Publication Year: 1961 , Page(s): 42  50Magneticcore memory elements characteristically require bipolar applied fields. The vanishing inner diameter of toroids and the loss of the third dimension entirely in deposited thin films demands minimization of the number of wires. A configuration which has been investigated and applied in a word organized memory at the University of California at Los Angeles is illustrated in Fig. 2. It consists of a pair of mutually inverted and parallel connected transistors. The transistors are not in general symmetrical. This paper discusses some of the system considerations which determine the important design parameters. Methods for location of regions of satisfactory operation in the manyvariable space of the inverted transistor pair are described. Although a particular design problem is discussed, attention is focused on the question, ``What classical and new procedures can we use to reduce the number of dimensions in such design problems?'' The power of the computer as a design tool is crucially dependent upon such processes. View full abstract»

47. HysteresisFree TunnelDiode Amplitude Comparator
Publication Year: 1962 , Page(s): 286  287
Cited by: Papers (2)First Page of the ArticleView full abstract» 
48. Current Steering in Magnetic Circuits
Publication Year: 1957 , Page(s): 21  30
Cited by: Papers (5)Magnetic switches are described in which the current from an energizing source is guided or steered through one out of many possible parallel branches, the conducting branch being selected by the presetting of appropriate magnetic elements. Only a few tubes are required for energization, and the outputs, obtained with reasonable efficiency, are substantially independent of exact circuit parameters. Current steering is achieved either by corediode combinations or by transfluxors. Decoding switches, of both types, for the selection of one outofmany outputs according to an input code are described in detail. A current of precise amplitude of the order of amperes is switched to a selected path in microseconds. Steered decoders are ideal for addressing core memories. A commutator switch for delivering sequentially a given current to a number of loads is described. Current steering makes possible simple magnetic counters and universal code converters. Experimental results of laboratory models of decoders and commutators are given. The principle of current steering broadens greatly the usefulness of magnetic switches by providing economy of associated electronic drivers and accuracy of switched currents. View full abstract»

49. A Synthesis Technique for Minimal State Sequential Machines
Publication Year: 1959 , Page(s): 13  24
Cited by: Papers (5)A method is presented which always yields a minimal state sequential machine satisfying a prescribed finite set of inputoutput sequences. An application is made to the case where a given sequential machine is to be reduced, by the merging technique, to a machine having the smallest number of states possible. Numerous examples are given. View full abstract»

50. Variable Time Delay by PadÃ© Approximation
Publication Year: 1961 , Page(s): 783First Page of the ArticleView full abstract»
Aims & Scope
This Transactions ceased publication in 1962. The current retitled publication is
Further Links
Persistent Link: http://ieeexplore.ieee.org/servlet/opac?punumber=5407885 More »
Frequency: 6
ISSN:
03679950
Subjects
 Computing & Processing (Hardware/Software)