Computers & Digital Techniques, IET
Latest Published Articles
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Behavioural synthesis utilising recursive definitions
Jan-07 2013 -
Comments on 'improving the speed of decimal division'
Jan-07 2013 -
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays
Jan-07 2013 -
Asymmetric large size multipliers with optimised FPGA resource utilisation
Jan-07 2013 -
Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique
Jan-07 2013
Popular Articles
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Image and video processing platform for field programmable gate arrays using a high-level synthesis
Jan-07 2013 -
High-performance low-power sensing scheme for nanoscale SRAMs
Jan-07 2013 -
Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation
Jan-07 2013 -
FPGA accelerator for floating-point matrix multiplication
Oct-25 2012 -
Asymmetric large size multipliers with optimised FPGA resource utilisation
Jan-07 2013
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Popular Articles (March 2013)
Includes the top 25 most frequently downloaded documents for this publication according to the most recent monthly usage statistics.-
1. Image and video processing platform for field programmable gate arrays using a high-level synthesis
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3. Fast and low overhead architectural transaction level modelling for large-scale network-on-chip simulation
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PDF (1271 KB)
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6. Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm technique
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PDF (372 KB)
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7. Advanced architecture optimisation and performance analysis of a reconfigurable grid ALU processor
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PDF (454 KB)
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9. Modelling and simulation techniques for highly integrated, low-power wireless sensor networks
Otis, B. ; Gambini, S. ; Shah, R. ; Steingart, D. ; Quevy, E. ; Rabaey, J. ; Sangiovanni-Vincentelli, A. ; Wright, P. |
PDF (607 KB)
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10. Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware
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PDF (823 KB)
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13. Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration
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PDF (740 KB)
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15. IRES: An integrated software and hardware interface framework for reconfigurable embedded system
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PDF (528 KB)
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16. Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays
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PDF (914 KB)
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18. Run-time stochastic task mapping on a large scale network-on-chip with dynamically reconfigurable tiles
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PDF (605 KB)
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19. Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits
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PDF (662 KB)
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23. VLSI architecture and chip for combined invisible robust and fragile watermarking
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PDF (460 KB)
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24. Decimal floating-point antilogarithmic converter based on selection by rounding: algorithm and architecture
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PDF (719 KB)
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25. Skewing-based method for reduction of functional crosstalk and power supply noise caused by on-chip buses
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PDF (754 KB)
Aims & Scope
Further Links
Aims & Scope
IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.
Persistent Link: http://ieeexplore.ieee.org/servlet/opac?punumber=4117424 More »
Frequency: 6
ISSN:
1751-8601
Subjects
- Computing & Processing (Hardware/Software)
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IET Research Journals
Michael Faraday House
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About this Journal
Author Resources
Title History
- ( 1994 - 2006 ) Computers and Digital Techniques, IEE Proceedings -
- ( 1980 - 1993 ) Computers and Digital Techniques, IEE Proceedings E
