Optimization of a retargetable functional simulator for embedded processors

The objective of this research is to develop tools and methods for system-level optimization of embedded software that is executed on system-on-chip platforms. In particular, this paper proposes a new instruction-set simulator's tool flow which has been extended with some retargetability features and multiple program representations. We propose an innovative way to improve the simulation speed, that is a key factor for embedded software optimization, by using a synthesis approach. In depth description is reported of the source-level optimization of the simulation library which is an important part of such new mechanism. Experimental results show a speedup of about 24 for the throughput of the simulation library, reaching the valuable performance of 50 Mops.