A sub-0.5 V dynamic threshold PMOS (DTPMOS) scheme for bulk CMOS technologies

A new dynamic threshold PMOS (DTPMOS) scheme is presented. In this scheme, the gate of a PMOS transistor is connected to its well in a conventional bulk CMOS technology. This technique results in improved switching speed compared to conventional CMOS in the sub-0.5 V regime. A 32-bit carry skip adder is designed for low voltage, low energy applications using the DTPMOS scheme. This adder consumes only 0.25 pJ of energy at a frequency of 5 MHz. The proposed design results in a 64% reduction in delay and 26% saving in energy compared to the conventional CMOS implementation.