A 64 MHz /spl Sigma//spl Delta/ ADC with 105 dB IM3 distortion using a linearized replica sampling network

The authors present a ΣΔ ADC with 105 dB distortion up to 1.5 MHz signal bandwidth, which uses a linear sampling network in a single-bit feedback 2-1-1 mash cascade modulator architecture. Operating at 64 MHz clock frequency, the measured SNR in a 1.1 MHz bandwidth is 88 dB. The area, including bypass capacitors, is 2.6 mm/sup 2/, in a 0.18 μm 1.8 V/3.3 V SP5M digital CMOS process. The power consumed is 230 mW, including references and decimation filter.