The 16 kB single-cycle read access cache on a next-generation 64 b Itanium microprocessor

A 16 kB four-ported physically addressed cache to be placed on a 64 b Itanium microprocessor operates at 1.2 GHz with 19.2 GB/s peak bandwidth. Circuit and microarchitectural techniques are optimized to allow a single-cycle read access latency. The cache occupies 3.2×1.8 mm/sup 2/ in a 0.18 μm CMOS process.