On signal-gating schemes for low-power adders

Signal gating schemes for low-power adder design are studied in this paper. Signal gating dynamically deactivates portions of an adder according to the actual precision of two operands. Based on program analysis, signal gating is developed for two different adders: symmetric adders and asymmetric adders. The effect of signal gating is investigated by incorporating several gating schemes into a RISC pipeline. Experimental results indicate more power saving compared to previous work.