A digitally controlled CMOS RF power amplifier

This paper presents the design, and implementation of an RF power amplifier in a standard 0.35 /spl mu/m CMOS technology. The amplifier is capable of delivering 16.5 dBm of output power at 1.85 GHz using a 3.3 V supply with an overall measured power added efficiency (PAE) of 30%. The power amplifier employs a class AB output stage, which represents a compromise between efficiency and linearity. Measurement results of the fabricated chip are included.