Formal verification and performance evaluation of logic integrated systems based on hierarchical analysis

Formal verification of very large scale integrated circuit (VLSIC) involves the formal correctness of the functionality of a given design, while circuit validation involves the reliability and efficiency of the design. A hierarchical approach for computation, of IC design efficiency is proposed and implemented using figures of merit. The work has been motivated to partially complete an IC formal verification tool. The implemented system is integrated into a formal verification environment to reflect the performance of the verified system. The system is capable of analyzing the power dissipation and figures of merit using equivalent R and C components. The hierarchical analysis and evaluation of figures of merit general factors obtained at different system levels represent performance evaluation of each gate. An illustrative example of a 6/spl times/6 carry look-ahead adder is given and worst case conditions have been determined. The system performance may thus be improved.