MT ARM: multithreading implementation in Arm7 architecture

The ARM7 processor can only reduce preserving and recovering overhead on context-switch, but it can do nothing about pipeline hazard. This paper presents one kind of multithreading implementation of ARM7 Architecture (called MT ARM) to achieve high-speed responsibility to handle events by eliminating the pipeline hazards. The pipeline of MT ARM is composed of four stages: Thread Select, Instruction Fetch, Decoder and Execution, which manage to handle external and internal events much more efficiently. Especially, the Thread Select stage is in charge of thread switching caused by all events. Synthesis of its VHDL implementation indicates that MT ARM costs no more than 5% in size and the power keeps almost the same compared with non-multithreading implementation of ARM7.