A hierarchical circuit extraction based on scan line

A method for hierarchical layout circuit extraction is presented. It uses double scan lines method to search for overlapping area between instances and physical layers, analyze the connectivity between the layers to obtain the transistors and the nets. This analysis is done from the bottom up, after obtaining the connectivity, it merges the nets connected through instances and obtains the correct hierarchical nets connection using a bottom up net search technique. The algorithm uses the properties of overlapping and the time to process overlapping is saved, it can process complex overlaps between instances, instance and geometry and also can be applied to layout extraction with large hierarchical level effectively. By using this method, the hierarchical net results can be obtained properly and efficiently.