QFP package analysis using partial element equivalent circuits

The partial element equivalent circuit (PEEC) technique is employed to model the electrical properties of the generic 64-lead quad-flat-pack (QFP). The model for the package includes many details, such as the leads, bonding wires and finite-size dielectrics. This model is used to investigate the parasitic effect of the package. As an example, the equivalent circuit is used to simulate the simultaneous switching noise (SSN) in conjunction with the devices on the chip.