An analytical linearization method for CMOS MMIC power amplifier using Multiple Gated Transistors

A novel analytical linearization method for CMOS MMIC power amplifiers based on parallel connection of transistors (also called Multiple Gated Transistors) is proposed. By this method, the power amplifier's IMD/sub 3/ can be eliminated analytically by operating the transistors within the determined g/sub m/" linearized range. In order to demonstrate the usefulness of the proposed method, a 900 MHz Class AB power amplifier using 4 NMOS transistors with maximum aspect ratio (W/L)=1300/0.5 is designed based on a 0.35 /spl mu/m CMOS process. The simulation results demonstrate that -76 dB IMD/sub 3/ can be obtained with 13 dB power gain.