An approach to reducing power consumption during delay test application

This paper presents an approach to reducing power consumption during delay test application. It is based on a re-ordering of the test-pairs in the test sequences to minimize the switching activity of the circuit-under-test during test application. Hamming distance between test-pairs is used to guide test-pair re-ordering. This guarantees a decrease in power consumption without reducing delay fault coverage. Experimental results are presented to demonstrate a reduction of the circuit activity for an average of 90.78% during test application.