Investigation of interface traps located at different regions in p-MOS transistors using DCIV technique

The interface traps located at different regions along the Si/SiO/sub 2/ interface, i.e., base channel (BC), drain junction-space-charge (JSC) and gate-drain extension (DE) overlap regions in p-MOS transistors are investigated by the newly developed direct-current current-voltage (DCIV) technique. When the gate voltage is swept from a low negative to a high positive value, two thermal recombination current peaks and one thermal-trap-tunneling (TTT) peak are formed, corresponding to the interface traps located at BC, JSC and DE regions, respectively. Interactions of interface traps located at different regions are observed when applying different kinds of stresses. The generation of interface traps in one region may cause reduction and migration of interface traps in another. This effect is interpreted by a hydrogen release and absorption model and may have profound influence upon device lifetime projection.