On-chip characterization of interconnect line-induced delay time in 0.15 /spl mu/m CMOS technology with 7-level metallization

A novel method is presented by which to perform on-chip characterization of interconnect line-induced delay time for ULSI circuit applications. Test chips were fabricated using 0.15 /spl mu/m CMOS technology using state of the art process techniques. The contribution of interconnect parameters, such as coupling capacitance and line resistance, on the delay time is extracted electrically in real time, free of ambiguity caused by geometric variation of metal lines. The delay time is modeled simply as a function of interconnect length. The extracted delay time equation enables easy and accurate prediction of chip performance. It is shown that the delay time induced by 3 mm and 5 mm interconnect lines is larger than pure gate delay by about 25 and 80 times, respectively.