Towards synthesis of monotonic asynchronous circuits from signal transition graphs

An approach to synthesis of asynchronous speed-independent circuits in monotonic logic gates (e.g. ASIC gate array library IBM SA-12E) is discussed. It is based on the normalcy conditions for STG behavioural specification, which guarantees implementability in monotonic and negative gates. The paper presents techniques for refining the STG specification to an implementable form. It is crucial that in comparison with other speed-independent synthesis methods, e.g. those in the Petrify CAD tool, this approach does not require the use of inverters with negligible delays in order to guarantee the absence of glitches or hazards in the circuits. Experiments with STG benchmarks, involving our new refinement techniques and VHDL simulation, indicate an average reduction of 28% in area and 23% in power consumption against solutions based on non-monotonic logic decomposition. These savings are more noticeable for more complex STG specifications. Such gains are however paid by an average of 6% decrease in circuit speed.