A 0.13 /spl mu/m full metal embedded DRAM technology targeting on 1.2 V, 450 MHz operation

We have developed a 0.13 /spl mu/m embedded DRAM technology, which targets high-speed and low-voltage operation, with logic performance fully compatible with 0.13 /spl mu/m pure logic. Parasitics (resistance, capacitance) of the DRAM macro limit its performances due to RC delay and IR drop. The parasitics of the new DRAM have been successfully minimized by employing the Full Metal embedded DRAM (FMD) technology which consists of a Metal-Insulator-Metal (MIM) capacitor with metal contact, and a newly developed low resistivity bitline. The results of performance simulation using a 16 Mbit DRAM macro show 1.2 V, 450 MHz of high-performance random access operation.