Noise and power reduction in filters through the use of adjustable biasing

A technique that enables the variation of bias currents in a filter without causing disturbances at the output is presented. Thus, the bias current can be kept at the minimum value necessary for the total input signal being processed, reducing the noise and power consumption. To demonstrate this approach, a dynamically biased log-domain filter has been designed in a 0.25-/spl mu/m BiCMOS technology. The chip occupies 0.52 mm/sup 2/. In its quiescent condition, the filter consumes 575 /spl mu/W and has an output noise of 4.4 nA rms. Signal-to-noise ratio greater than 50 dB over 3 decades of input and total harmonic distortion less than 1% for inputs less than 2.5 mA peak are achieved. The bias can be varied to minimize noise and power consumption without disturbing the output.