Preventing a "noisequake" [substrate noise analysis]

Substrate noise analysis can identify potential problems in mixed-signal and RF designs. In this paper substrate noise analysis was described and the methodology used in Cadence's SeismIC tool, a 3D solver, was discussed in detail. Several results were presented to demonstrate the accuracy of substrate extraction. Good correlation was shown between SeismIC and the 2D solver, Medici, for two structures in a TSMC 0.18 μm process. The overall average error in magnitude of the impedance for the two structures was 1.4 dB. Excellent correlation was demonstrated between SeismIC and measured impedances. The average magnitude of error between simulations and measurements was 6.4%. Another example of comparison of SeismIC with silicon was shown for a mixer fabricated in 0.6 μm technology. Measured gain showed excellent correlation to that simulated using a circuit simulator, with a substrate annotated netlist computed using SeismIC extraction. The SeismIC simulation flow was demonstrated for an Ethernet transceiver chip containing one million devices. This example shows the utility of using substrate analysis in the debug phase of a design, the value of identifying the worst noise contributors for a given design, and using analysis in the design phase to optimize the noise immunity of a design.