Design of fault-secure encoders for a class of systematic error correcting codes

In this paper, we consider the open problem of designing fault-secure encoders for various systematic error correcting codes (ECCs). The main idea relies on generating in parallel both the error correcting and detecting check bits. Then, the latter are compared against error detecting check bits which are regenerated from the former. The complexity evaluation of FPGA implementations of encoders with various degrees of parallelism shows that fault-secure versions compare favorably against their unprotected counterparts both with respect to complexity and the maximal frequency of operation.