Switch-level delay test of domino logic circuits

We address the testing of delay faults in domino circuits that contain complex gates. The different ways in which these faults can cause errors are demonstrated. We identify structures in both the evaluate and the precharge logic that should be tested for delay faults. We propose conditions to generate delay tests for them, and outline extensions to handle mixed static-domino circuits. Testability results are reported for benchmark circuits that are mapped to domino gates and in-house domino circuits.