Simulation of Georgia Tech's CMOS baseline using TSUPREM-4 and MEDICI

The Microelectronics Research Center of Georgia Tech has established silicon CMOS processing baselines as an important part of its research platform that provides supports to research communities around the world for research into numerous devices and fabrication techniques. Successful process runs include 1 /spl mu/m double polysilicon and double metal CMOS, 2 /spl mu/m double polysilicon and double metal CMOS, 2 /spl mu/m single polysilicon and single metal CMOS, and other CMOS based devices. This paper seeks to outline the simulation model for CMOS and NMOS designs. It includes a process simulator, TSUPREM-4, which was utilized to represent the process run parameters for the devices and a device simulator, MEDICI, which was employed to extract electrical characteristics. The simulation model has been utilized to observe general relationships between several processing parameters, such as the P+ and N+ doping concentrations as well as ion implantation energies and dosages, and corresponding threshold voltage variations.