Design of LNA at 2.4 GHz using 0.25 /spl mu/m technology

Two 2.4 GHz CMOS low noise amplifiers have been designed in a 0.25 /spl mu/m CMOS process. One is single-ended, and the other is differential. Both are fully integrated, without off-chip components. The design procedure and simulation results are presented in this paper. With a 3.3 V supply, the LNAs achieve power gains of 15 dB and 20 dB, noise figures of 2.2 dB and 2.4 dB, and third-order input intercept points (IIP3) of 1.3 dBm and 3.4 dBm. The power dissipations are 7.2 mW and 4.8 mW respectively. In the differential LNA design, a smaller die area is achieved using an LC tank to replace a large inductor.