Novel fault-tolerant adder design for FPGA-based systems

Proposes a novel fault-tolerant adder which is suitable for highly dependable systems implemented by means of field-programmable gate arrays (FPGAs). Compared to alternate conventional designs, the one presented here allows one to achieve fault-tolerance at lower design costs. A prototype has been developed, whose expected behavior has been verified by means of post-layout simulations and experimental measurements. Although our adder has been conceived for FPGA-based systems, it is also suitable to be implemented by means of VLSI and very deep sub-micron technologies.