A high performance 0.12 /spl mu/m CMOS with manufacturable 0.18 /spl mu/m technology

High-performance 0.12 /spl mu/m CMOS devices with manufacturable 0.18 /spl mu/m technology are presented. A nominal I/sub dsat/N/P of 950/410 /spl mu/A//spl mu/m at an I/sub off/ of 12 nA//spl mu/m is achieved by reducing the body effect. The double-sidewall structure developed can reduce gate-fringe capacitance without increasing the junction leakage, and the inverter delay of 11 ps/stage is achieved at a nominal L/sub gate/ of 0.12 /spl mu/m. Small 6T-SRAM cells of 3.1 /spl mu/m/sup 2/ with 0.5 /spl mu/m gate pitch are implemented using a vertical well isolation and a self-aligned contact (SAC). In the SAC process, a blanket Si/sub 3/N/sub 4/ layer used as an etching stopper is optimized for the I/sub dsat/N/P ratio and the negative bias temperature instability (NBTI) reliability. The 9-level interconnection is optimized to reduce a long wire RC-delay.