VLSI based tools for monitoring bus communication channels

An architecture for the run-time monitoring of the performance of a computer system is presented. In order to reduce the complexity of the system, a special integrated circuit has been designed, and the prototype integrated circuits are to be used in a first experimental realization of the system. The first prototype has been implemented in 3- mu m CMOS technology, contains 16 associative words, has a complexity of 11000 transistors, and has read/write and match times of 110 ns and 90 ns, respectively, due to a rather poor design of I/O pads. A second version in a 2- mu m technology is currently under fabrication and is expected to reduce these times by one half.<
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