Circuit synthesis evolution using a hardware-based genetic algorithm

We propose a scheme based on a hardware implementation of a genetic algorithm, to evolve the minimized logic solution of a defined input function. The minimization will be one of resource usage, more precisely of look-up tables (LUTs). The design aids in the difficult issue of technology mapping, as well as multi-level logic synthesis. The approach undertaken in this research involves intrinsic hardware evolution, where the circuit solution is evolved "online", and the output is a minimized structure of the circuit. Our architecture is outlined and discussed, while our current results are presented and analyzed.