CMOS outlier rejection circuit

An analog CMOS outlier rejection circuit is proposed in this work. The circuit calculates the instantaneous average current of an array of n analog input currents rejecting the outliers (the inputs which lie out of a desired percentage of the average current). Its structure includes an average circuit that provides the average current, and n outlier selector cells, able to identify and reject the low and the high outliers. The circuit is expected to be useful in parallel processing of signals from sensor arrays.