A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design

We developed a method for analyzing boron penetration and gate depletion using N/sup +/ and P/sup +/ dual-gate PMOSFETs. N/sup +/ gate PMOSFETs, which are immune to boron penetration and gate depletion, exhibited the threshold voltage shifts and fluctuation in P/sup +/ gate PMOSFETs. We found that V/sub th/ fluctuation in P/sup +/ gate PMOSFETs is dominated by boron penetration and that it is possible to select high-performance Gbit DRAM fabrication processes that are robust against V/sub th/ fluctuation.