A simulation study of CMOS performance improvement by laser annealed source/drain extension profiles

Laser thermal processing (LTP) dramatically changes the feasibility of ultra shallow and highly doped source-drain extensions (SDE). In comparison to conventional rapid thermal processing (RTP) profiles, steeper profiles and higher peak concentrations are achieved. This is of particular importance for sub-100 nm devices, where limited steepness of RTP profiles can result in significant source-drain resistance (Rsd) and severe short-channel effects. In this work we demonstrate that LTP technologies can reduce the source/drain resistance Rsd by more than 70% for Lpoly below 100 nm in both NMOS and PMOS. This leads to increases in saturation currents by up to 10%. Significant improvements in very deep submicron MOSFET performance can thus be expected as a result of this new technology being deployed.