Trapezoid-to-simple polygon recomposition for resistance extraction

Chip level resistance extraction has been carried out using heuristic functions based on layout object geometries. With prevalent hierarchical designs, layout objects on the same interconnect layer in subcells may well overlap in their parent cell. Resistance extraction based on geometrical heuristics as given by Hwang (1991) and Ladage et al. (1993), require polygons to be simple. As most layout extractors decompose polygons into trapezoids, we present a linear algorithm to recompose non-overlapping simple polygons from trapezoids. Resistance extraction can then be carried out on these simple polygons.