An AVPG for SOC design verification with port order fault model

Embedded cores are being increasingly used in the design of large system-on-a chip (SoC). Because the high complexity of SoC, the design verification is a challenge for system integrator. To reduce the verification complexity, the port order fault (POF) model has been used for verifying the core-based design. In this paper, we present a verification scheme and an automatic verification pattern generation (AVPG) system based on POF model.