A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems

This paper presents the design and implementation of a 160 Msample/s output, offset-compensated, linear-phase, frequency uptranslated Switched-Capacitor bandpass filter with 28.5 MHz midband frequency for a DDFS system. This bandpass system translates the 40 Msample/s, 11-12 MHz bandwidth signals from DDFS output to a higher 160 Msample/s, 28-29 MHz outputs with a 40 dB rejection of the unwanted frequency-translated signal bands. Special considerations and design in both circuit architectures and layout arrangements for dealing with non-ideal properties in realization of the high-speed analog and digital clock circuits will be discussed in terms of the speed relaxation, noise and mismatching reduction. The system is designed with 0.35 /spl mu/m CMOS technology and verified by behavioral, transistor-level and layout-extracted simulations. The active layout area occupies about 1.3 mm /spl times/2.7 mm and the circuit consumes about 138 mW for analog and 32 mW for digital at 3.0 V supply.