Behavioral test generation for VHDL processes

In this paper, two test generation algorithms for VHDL processes are presented. The first algorithm works on combinational processes, whereas the second works on sequential processes. The goal of both algorithms is testing all portions of the design by traversing all the possible paths. The VHDL subset we have considered in these algorithms covers almost 90% of ordinary designs. Our approach in this paper employs software testing metrics as well as state and transition coverage for FSMs.