Performance improvement for high speed devices using E-tests and the SPICE model

In order to improve the chip performance, a design or a process optimization occurs occasionally at the manufacturing stage. However modifying the design and the process through the real wafer processing of fabrication increases the time to market. This paper describes an efficient simulation approach for a new IC process centering method based on the SPICE model and E-tests (i.e., threshold voltage and saturation current). This methodology enables obtaining the optimal E-tests for improving the performance of high speed devices, before changing the real process conditions. In addition, the Response Surface Method (RSM) is used as a significant statistical tool for this new procedure. The validity and efficiency of this approach are proven by applying it to an IC process design centering problem for ALPHA CPU.