Noise analysis of monolithic RF balanced down conversion mixers

In this paper, noise features of monolithic RF balanced down conversion mixers are examined and analysed in detail with a periodic steady state simulator. The three kinds of port matching circuit architecture are proposed. Applying these optimum architectures to the single and double balanced down conversion (SBDC and DBDC) mixers can largely improve the mixers' performance. The valuable reference parameters were given in order to design low noise, low power consumption and high performance mixers. The validated mixers were designed by using a 25 GHz Si bipolar technology, which is under 2.7 V power supply, RF at 5.8 GHz, and IF at 100 MHz and 1 GHz, respectively. The conversion gain is better than 0 dB. The noise figure is lower 10 dB.