A static CMOS master-slave flip-flop experiment

A variant of a classical master-slave flip-flop based on transmission gates is derived where the transmission gates are replaced by static CMOS gates. The transmission gate flip-flop and the variant are evaluated along with one flip-flop based on C/sup 2/MOS latches and another based on SR latches. All flip-flops are edge-triggered. The propagation delay, set-up time, and hold time are estimated using a 0.35 /spl mu/m process. The author also investigates how the power dissipation at the maximal clock frequency varies when the supply voltage is scaled, both when the device geometry is kept constant and when it is scaled to yield good noise margins. In comparison, the variant on master-slave flip-flop has short propagation delay, but is only average in terms of throughput and power consumption. The flip-flop realized with C/sup 2/MOS latches seems to be a better candidate for a general-purpose implementation when voltage scaling is an option.