SiGe BiCMOS broadband phase-aligner circuit from 1 Gb/s to 11 Gb/s

The circuit is implemented as the interface between two BiCMOS chips for the TX frontend in second- and third-generation basestations. No clock recovery is necessary in these applications. The first chip translates the incoming IQ-data stream from the baseband into a serial output data stream with a bit rate up to 8.5Gb/s for CDMA-, GSM- and EDGE applications in the 2GHz range. This data stream already contains the antenna signal. To achieve this functionality, the first chip includes digital filters, interpolating stages and a /spl Sigma//spl Delta/ modulator. The second chip with input stage consisting of the presented phase-aligner circuit is a digital to analog converter (DAC).