Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip

Shows the feasibility of stacking SOI circuits to build 3D-ICs with dense vertical interconnects; the results are being applied to develop higher performance systems. Low-power circuits with three metal levels are fabricated with a 0.25/spl mu/m fully-depleted SOI technology. Three or more circuit layers are stacked and connected with 3D vias whose size, pitch, and resistance will be decreased by replacing the adhesive process with low temperature oxide bonding and utilizing tungsten plugs to fill high-aspect-ratio vias.