Universal-Vdd 0.65-2.0V 32 kB cache using voltage-adapted timing-generation scheme and a lithographical-symmetric cell

This 32 kB cache design operates from 120 MHz at 1.7 mW and 0.65V to 1.04 GHz at 530 mW and 2.0 V with a single internal supply using 0.18 /spl mu/m CMOS technology. The wide voltage operating range is achieved using a voltage-adapted timing-generation scheme with plural dummy cells and a lithographically-symmetric cell (LS-cell).