Fast physics based wafer-level reliability characterisation

A fast method for reliability evaluation and wafer level reliability measurements is presented. This method requires a physics-of-failure based approach. We propose pulsed electrical stress for reliability and thermal characterisation and present both experimental and theoretical results. An improved measurement set-up allows dynamic pulse-response measurement and direct parameter extraction. Dedicated analytical and numerical physical models have been developed. Step stress tests were carried out on HBT, Schottky diode and TLM structures. An extraction of electric field, internal temperature, carrier distribution and charge carrier temperature was performed, based on physical device models. Different device degradation mechanisms are analyzed and their relevance is discussed with respect to life-time calculation.